1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, it relates to a nonvolatile memory device constituted by combining a volatile memory cell and a nonvolatile memory cell including a floating gate circuit element.
2. Description of the Prior Art
Recently, in a static random access memory device (RAM), a volatile memory cell is combined with a floating gate circuit element to obtain a nonvolatile memory cell which is used to constitute a nonvolatile memory device. In a nonvolatile memory device of this type, the circuit configuration of each memory cell tends to be complex, and so the size of each memory cell tends to be large. However, this tendency leads to degradation in the reliability and integration of the memory device. In view of this problem, this tendency must be eliminated by a special circuit configuration or the like.
The prior art regarding this invention is disclosed in U.S. Pat. No. 4,300,212, and will be explained later in this text.
A primary object of the present invention is to provide a semiconductor memory device wherein the number of circuit elements is reduced, the area of a cell by which the device is constituted is reduced, high integration of the circuit is performed, and the number of tunnel capacitors which are the constituent elements are decreased, thereby increasing the production yield.
Another object of the present invention, is to increase the discretion of the layout design regarding the memory cell circuit.
Still another object of the present invention is to increase the storing efficiency by a plurality of write voltage applications.
According to the fundamental feature of the present invention, there is provided a semiconductor memory device comprising a volatile memory cell and a nonvolatile memory cell corresponding to the volatile memory cell, the nonvolatile memory cell comprising a transistor having a floating gate which turns on or off in response to the memorized data, a tunnel capacitor, with one electrode connected to the floating gate, a first write circuit connected to the other electrode of the tunnel capacitor, and a second write circuit capacitively coupled to one electrode of the tunnel capacitor. Either the first write circuit or the second write circuit supply a voltage for writing to the tunnel capacitor in response to the memorized data of the volatile memory cell, and electrons are injected into or emitted from the floating gate.
According to another feature of the present invention, there is provided a semiconductor memory device having a volatile memory cell and a nonvolatile memory cell corresponding to the volatile memory cell, wherein the nonvolatile memory cell comprises a tunnel capacitor with one electrode connected to a high-voltage control power source terminal, a first capacitor, with one electrode connected to the other electrode of the tunnel capacitor, a second capacitor connected between the other electrode of the first capacitor and the high-voltage control power source terminal, a transistor having a tunnel gate electrode with the gate connected to a common node between the tunnel capacitor and the first capacitor, and a switch means for controlling the potential at a common node between the first capacitor and the second capacitor in response to the memorized data of the volatile memory cell.
According to still another feature of the present invention, there is provided a semiconductor memory device having a volatile memory cell and a nonvolatile memory cell corresponding to the volatile memory cell, wherein the nonvolatile memory cell comprises a capacitor unit consisting of two series-connected tunnel capacitors, a series circuit of a first capacitor and a depletion-type or enhancement-type transistor connected between the common node of the two tunnel capacitors and a high-voltage control power source terminal, a transistor with the gate connected to the common node, and a switch means for controlling the potential of the gate of the depletion or enhancement-type transistor in response to the memorized data of the volatile memory.
According to still another feature of the present invention, there is provided a semiconductor memory device having a memory cell which comprises a pair of a volatile memory cell and a nonvolatile memory cell for saving the memorized data of the volatile memory cell, wherein the volatile memory cell comprises a capacitor portion for storing charges in response to data to be memorized, a transfer gate transistor connected between the capacitor and a bit line, a nonvolatile memory cell transistor having a double gate structure which has a control gate and a floating gate and in which electrons are injected by a tunnel effect, a recall transistor for transferring data stored in the nonvolatile memory cell transistor to the capacitor portion in response to a recall signal, a transistor turned on or off in response to the memorized data in the capacitor portion, a PGM transistor connected between the transistor turned on or off in response to the memorized data and the control gate, and a diode element connected to the control gate; wherein a first write voltage is applied to the control gate through the diode element, a second write voltage is applied to the drain of the nonvolatile memory cell transistor, and the PGM transistor is in a conductive state, whereby data of the volatile memory cell is written into the nonvolatile memory cell.